BISTed cores and Test Time Minimization in NOC-based Systems∗
نویسندگان
چکیده
This work discusses the role of BISTed cores in the test time reduction of NoC-based systems. A previously proposed technique that reuses network-on-chip for test purposes is used to define the optimum number of BISTed cores in the system, considering test time minimization and power consumption requirements. Experimental results show that not all of the embedded cores must have a self-contained test method to achieve a minimum global system test time.
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تاریخ انتشار 2003